A Schmitt-Trigger and Transistor Sizing based Optimization in Dynamic CMOS Circuits 1 A Schmitt-Trigger and Transistor Sizing based Optimization in Dynamic CMOS Circuits

One of the significantly used circuit style in highperformance VLSI systems is dynamic CMOS. With its principal advantage of implementing the evaluation logic only in pull down network, it offers a significant performance boost when compared to its static CMOS counterpart. However, the rising magnitude of circuits implemented on a chip, along with shrinking device size and process variations have increased the complexity of implementing dynamic CMOS circuit efficiently. Answering this challenge, this paper proposes an Schmitt-trigger and transistor sizing based optimization for dynamic CMOS circuits. This method operates through i) identifying significance of each timing path, and updating sizes of each transistor in the path; ii) operating the evaluation network and feedback keeper at lower supply voltage to reduce charging and discharging at dynamic nodes; and iii) using a Schmitt trigger to restore the low voltage swing at the dynamic node to normal levels at the design output. When tested through implementation on a IBM 90nm CMOS process, the proposed method has shown an improvement in worst-case delay by 40.64%, delay uncertainty by 49%, delay sensitivity by 28%, power consumption by 36%, and energy-delay-product by 77% when compared to their initial performances.